Transient Process Optimization for Dual-Arm Cluster Tools With Wafer Revisiting

Jipeng Wang,Chunrong Pan,Hesuan Hu,Liang Li

doi:10.1109/access.2021.3069888

Abstract

In wafer fabrication, it is imperative to minimize the transient process of cluster tools for the sake of on-demand and preventive maintenance. Due to the trend of multi-type and small-batch production, transient processes appear more and more frequently. Thus, the optimization problems of transient processes have gained increasing attention from both industry and academia. The requirement for wafer revisiting tend to complicate this problem significantly. However, only a few studies take such a challenge for cluster tools with wafer revisiting. This paper focuses on the schedule optimization of transient processes for dual-arm cluster tools with wafer revisiting. To accelerate transient processes, including both start-up and close-down ones, we adopt a program evaluation and review technique to analyze and harness a cluster tool’s state evolution. We then propose computationally efficient algorithms to speed up transient processes. Finally, we provide illustrative examples to show their applications and validate their effectiveness.

Highlights

To achieve higher quality, productivity, and yield, cluster tools with the single-wafer processing technology are widely applied in numerous semiconductor wafer fabrication processes, such as etching, chemical vapor deposition, and rapid processing technology with high temperature
After being loaded into a cluster tool through loadlocks, raw wafers are delivered into process modules (PMs) for processing in sequence according to pre-specified order, and return to loadlocks when all necessary processes are completed
The robot is equipped with one or two arms fixed in an opposite direction, leading to the single-arm cluster tool (SACT) and dual-arm cluster tool (DACT, see Fig. 1)

Summary

INTRODUCTION

Productivity, and yield, cluster tools with the single-wafer processing technology are widely applied in numerous semiconductor wafer fabrication processes, such as etching, chemical vapor deposition, and rapid processing technology with high temperature. Yang et al [28] develop efficient algorithms to find the optimal scheduling of SACTs with WRP and WRCTs. For the DACT with WRP, Wu et al [29] find that the system presents a three wafer cyclic process including three local and global cycles if the conventional swap strategy is applied. Kim et al [46] further present a maxplus algebra method to optimize the transient process of DACTs. Based on the ROPN model, Qiao et al [47] and Zhu et al [48] propose efficient algorithms to find the optimal schedule of SACTs with WRTCs during the SUTP and CDTP, respectively. With the system network model, we present computationally efficient algorithms to find the optimized transient process schedule for DACTs under diverse wafer revisiting cases. The state transformation from M1 to M3k+2 or from M2 to M3k+3 forms a periodic work cycle containing 3k − 3 local cycles and three global ones

SCHEDULING STRATEGY OF TRANSIENT PROCESSES

Initialization

ILLUSTRATIVE EXAMPLES

CONCLUSION