Abstract
AbstractTo simulate power circuits there is the difference admittance method DLV as well as the synchronised difference admittance method SDLV with factorised eigenvalues of the network branches. For all methods, deviations depending on the step size are generally unavoidable. Here, these deviations will be analysed by simple, single‐phase examples with the help of the Z‐transformation. With large step sizes, the standard DLV is falsified by oscillations, but not the SDLV. In contrast to DLV series connections of elements with SDLV does not lead to the same result as the simulation of the entire element. Nevertheless, the results achieved with SDLV3 are more precise than those with DLV.
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