Training Accelerator for Two Means Decision Tree

Abstract

Decision trees (DTs) are profusely used in machine learning (ML) applications on account of their fast execution and high interpretability. As DT training is time-consuming, in this brief, we proposed a hardware training accelerator to speedup the training process. The proposed training accelerator is implemented on the field-programmable gate array (FPGA) having a maximum operating frequency of 62 MHz. The proposed architecture uses a combination of parallel execution for training time reduction and pipelined execution to minimize resource consumption. For a given design, the proposed hardware implementation is found to be at least $14\times $ faster than the C-based software implementation. Moreover, the proposed architecture can be easily retrained for the next set of data using a single RESET signal. This on-the-go training makes the hardware versatile for any kind of application.