Traffic-aware reconfigurable architecture for fault-tolerant 2D mesh NoCs

Abstract

With the aggressive scaling of the VLSI technology, Networks-on-Chip (NoCs) are becoming more susceptible to faults. Therefore, designing reliable and efficient NoCs is of significant importance. The rerouting approach which is employed in most of the fault-tolerant methods causes the network performance to degrade considerably due to taking longer paths and creating hotspots around the faults. Moreover, they cannot adapt to the dynamic traffic distribution in the network. Considering the increasing demands for real-time systems, the necessity for designing reconfigurable and robust NoCs is even more pronounced. In this paper, a dynamically reconfigurable technique is proposed to address fault-tolerance and minimal routing in mesh NoCs. To accomplish this goal, the router architecture is modified to enable the frequently communicating nodes to bypass the faulty router and communicate through shorter paths. Thus, not only the rerouting is minimized, the connectivity of the network is maintained in the vicinity of faults. The experimental results validate the performance and reliability of the proposed technique with a small hardware overhead.