Trade-offs Between Gate Oxide Protection and Performance in SiC MOSFETs

Abstract

The reliability of gate oxides in SiC MOSFETs has come under increased scrutiny due to reduced performance under time dependent dielectric breakdown and increased threshold voltage instability. This paper investigates how 10% gate voltage (V GS ) derating in SiC MOSFETs can be implemented with minimal impact on loss performance. Using experimental measurements and electrothermal simulations of power converters, the trade-off between reduced V GS and conversion loss is investigated. It is shown that 10% V GS de-rating increases the ON-state resistance by 10% and the turn-ON switching energy by 7% average while the turn-OFF switching energy is unaffected. The low temperature sensitivity of the ON-state losses in SiC MOSFETs can be exploited since the rise in junction temperature due to V GS derating is marginal, unlike Si devices where ON-state resistance rises significantly with temperature. The load current and switching frequency influences the effectiveness of V GS derating. It is also shown that reducing the gate drive output impedance can compensate for V GS derating at high switching frequencies, with reduced total loss penalization. This may be important for protecting the gate oxide and enhancing its reliability.