Trade-offs among power consumption and other design parameters of two-stage recycling folded cascode OTA that using embedded cascode current buffer compensation technology

Abstract

Being able to solve specific issues and meet specific requirements are the goals of designing a two-stage OTA, but how to optimize the trade-offs among its various performances is another key issue. Conventional two-stage folded cascode operational transconductance amplifier (FCOTA) with Miller compensation is the most commonly used circuit structure, but its low current efficiency makes it less advantageous in terms of the trade-off. Thus in this paper, the two-stage recycling folded cascode OTA (RFCOTA) is introduced for lower consumption without degrading other performances and the embedded cascode current buffer (ECCB) compensation is employed which further increases the phase margin compared to Miller compensation without additional power consumption and chip areas. This shows the two-stage RFCOTA has a more comprehensive optimization of various design trade-offs related to power consumption. The Miller compensated two-stage FCOTA and ECCB compensated two-stage RFCOTA are designed and realized in a 0.18 μm CMOS technology and simulation results show that the RFCOTA has the phase margin enhancement of 7° and 8 dB improvement in dc-gain as well as increase slew rate of 2.16 V/us under the condition of halving power consumption compared with conventional FCOTA.