TRACK: An algorithm for fault-tolerant, dynamic and scalable 2D mesh network-on-chip routing reconfiguration

Abstract

Network-on-chip (NoC) is a reliable and scalable on-chip interconnect solution particularly used for MPSoCs and CMPs. Increasing susceptibility of NoC to failures is becoming a new research concern. Failures in components such as on-chip link or router may disrupt the underlying routing function. Reconfiguration of routing function is required to sustain network connectivity while maintaining deadlock-freedom in event of failure(s). Existing approaches either use routing tables or meta-data or involve all network nodes for participation in the reconfiguration process. This paper proposes TRACK, an algorithm for fast and scalable routing reconfiguration. It uses logic-based routing instead of tables and identifies affected nodes (i.e., rows/columns of mesh network) by single and double-link failures. In the proposed algorithm, reconfiguration is needed only for the affected nodes and the remaining network can continue to work. TRACK outperforms the existing one and reduces latency up to 42% and improves throughput up to 22% for single and double-link failures in 8 × 8 2D mesh network-on-chip. By employing logic-based routing, hardware cost is also reduced, i.e., 30% in area and 29.5% in power overhead for a 16 × 16 mesh router.