Trace Cache Miss Rate

Abstract

Instruction fetch mechanism is a performance bottleneck of Super-scalar and Simultaneous Multithreading Processors. A hardware mechanism, known as Trace Cache, is used in several processor architectures to improve instruction fetch performance. Most studies on Trace Cache architectures are based on simulation of benchmark programs. Analytical studies on Trace Cache and Trace Cache Miss Rates are rare. This paper presents a new analytical model of Trace Cache Miss Rate. The presented model can be used to understand performance and tradeoffs in Trace Cache design. The presented study is the first of its kind, which provides clearer understanding of Trace Cache performance for designers, students, and researchers.