同步TP RAM的低功耗设计方法

Abstract

针对SoC中同步TP RAM的功耗较大问题，提出一种设计方法。通过将SoC中的同步TP RAM替换成SP RAM，在SP RAM外围增加读写接口转换逻辑，使替换后的RAM实现原TP RAM的功能，保持对外接口不变。为了进一步降低功耗，对地址总线进行格雷编码，采用动态电压调整技术及合理的电源分区策略。将文中方法应用于一款多核SoC芯片，经TSMC 28 nm HPC工艺实现。仿真结果表明：优化后的RAM面积减少了24.76%，功耗降低了44.89%。 As the power consumption of synchronous TP RAM in SoC is large, a new design method of opti-mization is proposed. In order to achieve the function of the original TP RAM and keep the exter-nal interface unchanged, TP RAM is replaced with SP RAM, and read-write interface logics of con-version are added around SP RAM. For less power, address bus is encoded through Gray code; dynamic voltage regulation and reasonable power partition strategy are used. The method discussed in this paper is used in the multi core SoC chip which has been implemented in TSMC 28nm HPC process. The simulation results indicate that the area of optimized RAMs is reduced by 24.76%, and the power saving is reduced by 44.89%.