Abstract
In this paper, the idea of variable resolution ADCs is proposed and implemented for all types of ADC architectures. A novel peak-detector circuit is employed to achieve variable resolution as well as to switch the unused sections of the ADCs to standby mode. Linear reduction in resolution leads to exponential reduction in power. The ADCs are capable of operating at 4–12 bit precision at a supply voltage of 2.5V. The sampling frequency ranges from 1.8MSPS to 1.2 GSPS that depends on ADC topologies. Variable-resolution flash, semi — flash, pipelined and SAR ADCs operating at a maximum resolution of 8-bit, 12-bit, 12bit, 10-bit respectively have been designed and verified for post layout simulations in standard 65nm CMOS technology.
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