Towards Polynomial Formal Verification of AI-Generated Arithmetic Circuits

Abstract

The popularity of Artificial Intelligence (AI) is growing in many domains. The designers have started to use AI in Electronic Design Automation (EDA) for the generation of highly optimized digital designs, particularly arithmetic circuits. The arithmetic blocks generated by deep and reinforcement learning usually outperform the generic architectures in terms of design characteristics such as area, delay, and power. As a result, it is expected that AI-generated arithmetic circuits will soon occupy an important place in many applications thanks to their highly efficient architectures. A crucial task after designing an arithmetic circuit, including AI-generated circuits, is verification. Formal methods can detect faulty designs before fabrication and prevent financial loss and disastrous consequences. Despite the huge progress of formal methods in verifying a wide variety of designs, their time and space complexity is not fully investigated, particularly for the AI-generated arithmetic circuits. In this paper, we calculate the complexity bounds for formal verification based on Binary Decision Diagrams (BDDs) when they are used to ensure the correctness of general prefix adders. We prove that the Polynomial Formal Verification (PFV) of a prefix adder is possible independent of the prefix tree structure. Our proof is valid for both regular prefix adders generated by known algorithms and irregular prefix adders generated by AI.