Abstract
Channel emulation is widely used to control wireless channels and replay scenarios for repeatable experimentation and evaluation. Characterizing the propagation of massive Multiple-Input Multiple-Output (MIMO) systems, is challenging due to the rapid scaling of the number of channels needed to create representative scenarios as well as accurately modeling complex interdepedencies that exist within the channel matrix. Nonetheless, having the ability to emulate massive MIMO channels is critical for the development and testing of next-generation cellular protocols and algorithms. To achieve such scale for massive MIMO channel emulation solutions, in this paper, we study the tradeoff in channel emulation fidelity versus the hardware resources consumed using both analytical modeling and FPGA-based implementations. To reduce the memory footprint of our design, we optimize our channel emulation using an iterative structure to generate geometry-based channels at scale. In addition, the effects of varying the channel update rate and word length selection are evaluated in the paper and can significantly improve the implementation efficiency on an FPGA.
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