Towards Efficient Input Space Exploration for Falsification of Input Signal Class Augmented STL

Abstract

In recent years black-box optimization based search testing for Signal Temporal Logic (STL) specifications has been shown to be a promising approach for finding bugs in complex Cyber-Physical Systems (CPS) that are out of reach of formal analysis tools. The efficacy of this approach depends on efficiently exploring the input signal space, which for CPS is infinite. In this work, we present a framework for more efficient exploration of the input space for falsification of a class of engineering requirements. Our first contribution is a dimensionality reduction heuristic for optimization based falsification frameworks for dynamical systems over this augmented logic. This heuristic leverages the step response of the system - a standard system characteristic from Control engineering - to obtain a smaller time interval in which the optimizer needs to vary the inputs. Next, we note that system behaviors on a standard class of inputs such as on step inputs or sinusoids are often of paramount importance to engineers, and such inputs while easy to specify as functions, are difficult for temporal logics to capture. Our second contribution is a formalism to augment a commonly used fragment of Signal Temporal Logic (STL) to incorporate such signals for use in a black-box optimization based falsification framework. Finally, we demonstrate the effectiveness of our approach in falsification of temporal logic specifications on three case studies over complex Simulink models.