Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors

Abstract

To meet the ever increasing processing demand, we have more number of components in modern Chip MultiProcessors (CMPs). This leads to increased on-chip power density resulting in prohibitive chip temperatures. The increased chip temperature not only increases the cooling cost, but it also increases leakage power dissipation, which in turn increases chip temperature. On-chip caches that occupy the largest onchip area are usually assumed as a cooler on-chip portion. However, this is a misconception as a recent study shows 30°C spatial temperature variance in modern large on-chip caches. This paper attempts to reduce the effective chip temperature by intelligently turning off/on some on-chip Last Level Cache (LLC) banks in a tiled CMP during process execution. The turned off cache banks will act as on-chip thermal buffers helping to reduce the effective chip temperature. Resizing decision will be taken based upon generated cache hotspots or performance. With a negligible performance overhead simulation results show a reduction of 4°C in the chip temperature with 52% maximum savings in cache leakage.