Towards architectural support for bandwidth management in mixed-critical embedded systems

Abstract

Mixed-critical platforms require an on-chip interconnect and a memory controller capable of providing sufficient timing independence for critical applications. Existing real-time memory controllers, however, either do not support mixed criticality or still fail to ensure negligible allow a certain degree of interference between applications. On the other hand, Networks-on-Chip manage the traffic injection rate mainly by employing complex techniques; either back-pressure based flow-control mechanisms or rate-control of traffic load (i.e. traffic shaping). This work proposes such a Traffic Shaper Module that supports both monitoring and traffic control at the on-chip network interface or the memory controller. The advantage of this Traffic Shaper Module is that at system level it provides guaranteed memory bandwidth to the critical applications by limiting traffic of non-critical tasks. The system is developed in the Xilinx ZYNQ7000 System-on-Chip while the measurements were captured on a Zed-board development board. By enabling the Traffic Shaper in our architecture we achieved fine-grain bandwidth control with negligible overhead, while providing bandwidth of only 0.5-5 percent less than the theoretical specified bandwidth.