Towards a Scalable Test Solution for the Analysis of Interconnect Shorts in On-chip Networks

Abstract

Traditional bus-based systems-on-chip (SoCs) are turned to on-chip networks (NoCs) to overcome communication bottleneck. But, fabricating such NoC-based systems without any defect in interconnects or logics is a major challenge. This paper proposes a cost effective and scalable on-line test solution that detects and diagnoses intra-and inter-shorts in NoC interconnects. The proposed solution offers constant test time with general NoC topologies, and channel widths considering little hardware area and performance overheads. Simulation results establish the effectiveness of the proposed solution. We see that the test time is reduced by 0.5–11.25x achieving 100% coverage metrics. Simulation results also reveal the significant effect of interconnect shorts on network performance at large traffics. We see that our test solution improves packet latency by 14.98–40.57% and reduces energy consumption of a packet flit by 6.83–31.19%.