Abstract
The Medipix3 Collaboration has broken new ground in spectroscopic X-ray imaging and in single particle detection and tracking. This paper will review briefly the performance and limitations of the present generation of pixel detector readout chips developed by the Collaboration. Through Silicon Via technology has the potential to provide a significant improvement in the tile-ability and more flexibility in the choice of readout architecture. This has been explored in the context of 3 projects with CEA-LETI using Medipix3 and Timepix3 wafers. The next generation of chips will aim to provide improved spectroscopic imaging performance at rates compatible with human CT. It will also aim to provide full spectroscopic images with unprecedented energy and spatial resolution. Some of the opportunities and challenges posed by moving to a more dense CMOS process will be discussed.
Highlights
Tiling larger areas using Through Silicon ViasVertex detectors for high energy physics and X-ray detectors for synchrotron light applications require large and preferably contiguous hermetically covered sensitive areas
Digital column readout architectures for hybrid pixel detector readout chips T Poikela, J Plosila, T Westerlund et al Atom-Probe Field-Ion Microscopes and High-Field Surface Effects Erwin W
When charge summing and allocation is switched off the energy information is almost completely lost because of charge sharing but when charge summing is switched on spectroscopic information becomes again visible
Summary
Vertex detectors for high energy physics and X-ray detectors for synchrotron light applications require large and preferably contiguous hermetically covered sensitive areas. Since the chips are to be bump bonded to sensors after TSV processing, a unique requirement for these wafers was that Under Bump Metallisation (UBM) had to be deposited on the front side passivation openings (about 25 μm diameter) prior to rear side processing Another complication is that in the ASIC process used for these chips the top metal layer is not planarised and the surface of the wafers had steps of 4 μm corresponding to the pattern of the top metal. Once again UBM was deposited on the front of the wafers and the IO pads were connected using TSVs to the array of BGA compatible pads on the rear side of the chip The aim of this project was to evaluate the yield of the TSV processing.
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