Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems

Emilio Pérez-Bosch Quesada,Markus Andreas Schubert,Mamathamba Kalishettyhalli Mahadevaiah,John Reuben,Francisco Jiménez-Molinos,Juan Bautista Roldán,Rocío Romero-Zaliz,Christian Wenger,Eduardo Pérez

doi:10.3390/electronics10060645

Abstract

In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.

Highlights

Considering the successful development of software-implemented Artificial NeuralNetworks (ANN) and their increasing integration in the commercial market, it is of special interest to consider the subsequent drawbacks that the performance of these kind of neuro-inspired networks entails
This behavior is featured by the transition from a single high resistance state (HRS) to three different low resistance states (LRS) and vice versa by modifying the compliance current imposed by the NMOS transistor during the
Three physics-based compact models for RRAMs were studied and verified with experimental data to validate their capability to simulate the multilevel behavior of the 1T-1R cells

Summary

Introduction

Considering the successful development of software-implemented Artificial Neural. Networks (ANN) and their increasing integration in the commercial market, it is of special interest to consider the subsequent drawbacks that the performance of these kind of neuro-inspired networks entails. The implementation of RRAM cells as synaptic unions between artificial neurons allows the possibility to design and carry out ANNs featured by low-power consumption and low integration area [8]. This is possible due to the multilevel approach known as Multi-Level Cell (MLC) behavior, consisting of modulating in multiple states. The existence of a gap between the device and circuit/system levels challenges the implementation of hardware-based ANN, the development of accurate and time-efficient RRAM models for circuit design simulations is an issue that must be tackled.

Compact Models Description

Stanford-PKU Model Extended with Multilevel Capability

Experimental Samples Characteristics

Modeling Results and Discussion

A Neural Network Study to Assess the Multilevel Approach

Conclusions