Toward determining optimal mechanical properties in adhesives for flip chip and wire bonded low-k die

Abstract

Even for an industry accustomed to dramatic and tumultuous change, the move of IC and packaging fabs toward low-k dielectric is remarkable for its technical challenges and public drama. The new dielectrics exhibit poor adhesion and mechanical strength, rendering many pre-existing materials and processes ineffective at ensuring cost-effective manufacturing of reliable IC packages. IC and packaging fabs are working together at unprecedented levels to ensure technical dominance and competitive cost structures. This paper will provide a snapshot of modeling and experiments in progress to identify critical mechanical properties of underfills, encapsulants and die attach pastes leading to satisfactory preconditioning and thermal cycling performance in flip chip and wirebonded PBGAs. A number of divergent views are found within different organizations as to the combination of properties giving the best performance. Glass transition temperature, modulus, CTE, adhesion and cure shrinkage are critical properties. There is no certainty that a given combination of properties will lead to a universal product applicable for a variety of die sizes, reflow temperatures and reliability specifications. Available data suggests that the challenge to material designers centers, as always, on a balance of material properties. Flip chip packages require underfills that are stiff enough to reinforce solder joints at elevated temperatures, yet soft enough to cradle the delicate dielectric. Warpage is a looming issue for these packages as for the wirebonded PBGAs. Questions concerning effects of die attach on PBGA performance need to be addressed.