Abstract
The total ionizing dose irradiation effects are investigated in Si vertical diffused MOSFETs (VDMOSs) with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer. Radiation-induced holes trapping is greater for single SiO2 layer than for double Si3N4/SiO2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO2 at lower oxidation temperature. Gate bias during irradiation leads to different VTH shift for different gate dielectrics. Single SiO2 layer shows the worst negative VTH at VG=0 V, while double Si3N4/SiO2 shows negative VTH shift at VG=-5 V, positive VTH shift at VG=10 V, and negligible VTH shift at VG=0 V.
Highlights
Silicon power MOSFET, especially vertical diffused MOSFET (VDMOS), is widely used for high power application due to its mature technology and cost efficiency
VDMOS is often used under harsh environment such as space, where it suffers from cosmic radiation [1,2,3,4]
We investigate total ionizing dose (TID) effects in Si VDMOS with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer, different oxidation temperatures of SiO2, and different gate bias during irradiation
Summary
Silicon power MOSFET, especially vertical diffused MOSFET (VDMOS), is widely used for high power application due to its mature technology and cost efficiency. VDMOS is often used under harsh environment such as space, where it suffers from cosmic radiation [1,2,3,4]. To operate normally in space environment, Si VDMOSs must be able to withstand ionizing radiation such as total ionizing dose (TID). We investigate TID effects in Si VDMOS with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer, different oxidation temperatures of SiO2, and different gate bias during irradiation
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