Topology comparison and design optimisation of the buck converter and the single-inductor dual-output converter for system-in-package in 65nm CMOS

Abstract

Portable electronic devices, such as laptop computers and personal portable electronic devices are battery-powered and need power-electronics converters as an interface between the battery and the load. To ensure a long battery life, it is important that the power-electronic converters operate at high efficiency. The volume available for power electronics is limited which necessitates the use of integration technologies to achieve high-power-density converters. Integrating passive components in silicon makes monolithic integration of power converters in system-on-chip difficult and hybrid integration in the form of system-in-package where passive components are implemented in alternative technologies and integrated in the package seems to be a more feasible option at present. High operating frequencies, necessary for the reduction of the passive components size results in the increase of switching losses in the power semiconductors which negatively influences the efficiency. Furthermore, power semiconductor losses are directly dependent on the chip size which in turn influences the cost of the converter. Also, the losses are dependent on the time waveforms of electrical currents and voltages which in turn depend on the chosen circuit topology. The paper presents a topology comparison and a design optimization procedure for the implementation of a DC-DC converter (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</inf> 3V− 4.2V from Li-ion battery, V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</inf> 0.6V−1.2V, load current≪ several 100mA). It is assumed that the active part of the converter is implemented in 65nm CMOS technology. A high-level topology evaluation based on several criteria such as efficiency, cost, technology feasibility and size is presented. The design procedure for maximum integrated DC-DC converter efficiency by means of finding optimum transistor widths is presented and illustrated on two topologies.