Abstract
The qubit-mapping problem aims to assign and route qubits of a quantum circuit onto a NISQ device in an optimized fashion, with respect to some cost function. Finding an optimal solution to this problem is known to scale exponentially in computational complexity; as such, it is imperative to investigate scalable qubit-mapping solutions for NISQ computation. In this work, a noise-aware heuristic qubit-assignment algorithm (which assigns initial placements for qubits in a quantum algorithm to qubits on a NISQ device, but does not route qubits during the quantum algorithm's execution) is presented and compared against the optimal \textit{brute-force} solution, as well as a trivial qubit assignment, with the aim to quantify the performance of our heuristic qubit-assignment algorithm. We find that for small, connected-graph algorithms, our heuristic-assignment algorithm faithfully lies in between the effective upper and lower bounds given by the brute-force and trivial qubit-assignment algorithms. Additionally, we find that the topological-graph properties of quantum algorithms with over six qubits play an important role in our heuristic qubit-assignment algorithm's performance on NISQ devices. Finally, we investigate the scaling properties of our heuristic algorithm for quantum processors with up to 100 qubits; here, the algorithm was found to be scalable for quantum-algorithms which admit path-like graphs. Our findings show that as the size of the quantum processor in our simulation grows, so do the benefits from utilizing the heuristic qubit-assignment algorithm, under particular constraints for our heuristic algorithm. This work thus characterizes the performance of a heuristic qubit-assignment algorithm with respect to the topological-graph and scaling properties of a quantum algorithm which one may wish to run on a given NISQ device.
Highlights
Quantum computation may still be in its infancy, but new advances have allowed for the first experimental demonstrations of quantum computing in recent years [1], [2], [3], [4], [5]
Heuristic qubit-assignment algorithms lack a systematic comparative basis by which their performance can be assessed; this includes the notion of providing upper and lower bounds for the performance of a quantum algorithm executed on a NISQ device, evaluating quantum circuits whose entangling two-qubit gates produce interaction graphs with different topological graph-theoretic structures, and understanding whether or not a given heuristic qubit-assignment algorithm will scale well as both the quantum algorithm and the QPU size are increased. The purpose of this manuscript is to answer the following questions: i) how does a HQAA compare relative to an optimal brute-force and a trivial approach to the qubitassignment problem, ii) do the topological features of a quantum algorithm influence the measured success rate for a noise-aware HQAA, and iii) What behavior can one expect from a noise-aware HQAA as the size of the QPU is scaled up? To this end, we develop an HQAA which is similar to the noise-aware one introduced in [50], but improve upon this work by incorporating notions of graph centrality [56], [57]
In the context of the qubit-mapping problem, we consider two objects: an interaction graph (IG), which is a graph representation of the quantum circuit that we would like to execute, and the coupling graph (CG), which is a graph representation of the QPU’s geometric connectivity
Summary
Quantum computation may still be in its infancy, but new advances have allowed for the first experimental demonstrations of quantum computing in recent years [1], [2], [3], [4], [5]. Quantum compilers must perform several steps in order to prepare the quantum algorithm for actual execution on a device. Speaking, these steps are: 1) to decompose the quantum gates into elementary gates; 2) to assign the qubits of the quantum circuit to the physical qubits of the quantum processor, and inserting SWAP operations (known as routing) into the algorithm in order to satisfy the connectivity constraints of a given quantum device; 3) and to optimize the resultant quantum circuit, with an aim to minimize quantities such as the execution time and gate count, among other cost functions. Two graphs are termed topologically equivalent if there is a map f : X → Y between two graphs X and Y such that the following conditions are upheld [59]: 1) The map f is bijective, i.e. f maps from all edges to all edges and from all vertices to all vertices; 2) f is continuous, i.e. f is an isomorphism from X to Y , allowing for the graph operations of smoothing out and subdivision of edges; and
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