Abstract
AbstractToday’s compute node architectures leverage impressive performance by offering more parallel resources on the chip as well as on the node level. Among parallel resources are memory interfaces (ccNUMA), cores, caches and data parallel execution units. On the other hand modern multicore designs also exhibit shared resources such as memory bandwidth on the chip level, last level cache bandwidth and capacity, and access to the network interface. An additional performancelimiting factor is the frequently high cost for synchronization. The task to make full use of parallel resources while keeping an eye on the bottlenecks imposed by the shared resources is non-trivial. Common programming models often address issues related to parallel programming in general while not covering topological issues introduced by multi- and manycore architectures. The industry is still pushing forward introducing even more powerful manycore systems like, e.g., the Nvidia Kepler and Intel MIC architectures.KeywordsShared ResourceMemory BandwidthNode LevelMulticore SystemTransactional MemoryThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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