Top-Down Simulation Methodology of a Mixed-Signal Read Channel Using Standard VHDL

Abstract

This paper presents a mixed-signal system modeling and simulation methodology using an event-driven simulator that supports real-valued signals, such as standard VHDL. Success of this methodology has been demonstrated by a commercial 550 MHz Partial Response Maximum Likelihood (PRML) magnetic recording read channel. The read channel IC is of mixed-signal design type with 30% analog and 70% digital content. The digital portion has been synthesized from the RTL subset of VHDL (1987 standard). The analog part has been behaviorally modeled using the 1993 standard version of VHDL. Five abstraction levels of digital circuits modeling are also described.