Top Level Bus Estimation for Hierarchical Design

Abstract

As technology advanced into deep sub-micron era, hierarchical design is employed more and more to overcome the growing complexity. Top level timing is a key challenge in deciding the chip performance and time to market. Data bus talks between sub-modules are considered as the bottleneck for top physical designer. An early estimation on these buses will provide good evidence for pipelining in front-end design and buffering in back-end design and also guide the later-on routing for the related nets. This paper proposed a fast estimation algorithm to model the routing of bus talks between sub-modules. First, a grading step is used to decide the criticality for each data talk, according to their bus width and timing criticality. Then, a new connection model is put forward to simplify routing channels on top level without losing too much accuracy. After the simplification, an undirected graph will be built to describe all the routing blockages. Therefore, finding a point-to-point path avoiding blockages on top level becomes polynomial time complexity and the optimum is achievable. Congestion is considered as well. Compared with recent grid-based work which also approximates path finding problem, the proposed graph is smaller and thus faster. Using the path finder, all the data talks will be dynamically estimated one by one at last. Taking practical designs as benchmarks, the algorithm runs steady and fast for the current design scale. Moreover, the undirected graph in this work can be extended to solve other issues as well.