Abstract
In this letter, top-gate electric-double- layer (EDL) indium–zinc-oxide (IZO)-based synaptic transistors were demonstrated. A silicon oxide solid electrolyte film was used as the insulator, which was deposited by the plasma-enhanced chemical vapor deposition method at room temperature. A low operation voltage of 1 V was achieved due to the formation of the EDL layer at the SiO2/IZO interface. In the top-gate synaptic transistors, paired-pulse facilitation and high-frequency filter were mimicked, which are the short-term synaptic behaviors. Standard microfabrication processes were used to pattern, which could be used for large integration in the future.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
