Tombstone Initiation Model for Small Form-Factor Surface Mount Passives

Abstract

Passive components such as capacitors are shrinking in size in electrical systems in tandem with the device transistor features. With the size shrink comes an increased risk of process-induced defects such as capacitor tombstoning or billboarding. These defects involve poor connectivity of capacitor terminations to the substrates, affecting the electrical performance of the system. We have developed an analytical model to predict the probability of such defects to occur as a function of the design and process factors. The model demonstrates that the surface tension at component terminals dominates over the inertia forces (component weight) in case of components with submilligram weight. Bulkier capacitors have lower risk of tombstoning compared to the lighter ones. The analysis also points to other modulating factors such as component termination width, component height, solder pad size, and the solder paste volume. We also present the experimental results on small form-factor components that confirm some of the predictions for the model. Optimum design guidelines for the electrical systems with soldered components can be obtained from the current model.