Token-Aware Completion Functions for Elastic Processor Verification

Sudarshan K Srinivasan,Rajendra S Katti,Koushik Sarker

doi:10.1155/2009/480740

Sudarshan K Srinivasan, Rajendra S Katti + Show 1 more

Open Access

https://doi.org/10.1155/2009/480740

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Journal: Research Letters in Electronics	Publication Date: Jan 1, 2009
Citations: 10	License type: CC BY 3.0

Affiliation: North Dakota State University

Abstract

We develop a formal verification procedure to check that elastic pipelined processor designs correctly implement their instruction set architecture (ISA) specifications. The notion of correctness we use is based on refinement. Refinement proofs are based on refinement maps, which—in the context of this problem—are functions that map elastic processor states to states of the ISA specification model. Data flow in elastic architectures is complicated by the insertion of any number of buffers in any place in the design, making it hard to construct refinement maps for elastic systems in a systematic manner. We introduce token-aware completion functions, which incorporate a mechanism to track the flow of data in elastic pipelines, as a highly automated and systematic approach to construct refinement maps. We demonstrate the efficiency of the overall verification procedure based on token-aware completion functions using six elastic pipelined processor models based on the DLX architecture.

Highlights

The impact of persistent technology scaling results in a previously ignored set of design challenges such as manufacturing and process variability and increasing significance of wire delays
The idea with the verification approach is to show that the elastic processor correctly implements all behaviors of its instruction set architecture (ISA) model, which is used as the high-level specification for the processor
It is sufficient to prove that the elastic processor and its ISA satisfy the following core Well-Founded Equivalence Bisimulation (WEB) refinement correctness formula to establish that the elastic processor refines its ISA

Summary

Introduction

The impact of persistent technology scaling results in a previously ignored set of design challenges such as manufacturing and process variability and increasing significance of wire delays. The very attractive property of elastic systems is that they allow for the insertion of buffers (known as elastic buffers) in any place in the data path to deal with propagation delays of long wires, without altering the functionality of the system The insertion of these buffers can drastically change the data flow patterns of the system, making it hard to compute refinement maps for these systems. We request the reader to refer to literature for background on synchronous elastic networks [2, 3] and refinement [4] Note that this is the first known approach that aims to verify the correctness of elastic pipelined processors against their high-level nonpipelined ISA specifications. We have developed an equivalence checking approach that is used to verify elastic pipelines against their synchronous parent pipelines [7]

Elastic Processor Models

Token-Aware Completion Functions

Results

Conclusions