Abstract
The aim of this paper is to present proper ways of VHDL modelling for a TMS320C203 system, containing a flash memory, and a SRAM. During the research models for all the blocks of the microprocessor system, along with experimental results have been produced. Models for SRAM and Flash memory have been researched, as well. The overall model can be verified with a boundary scan test. This paper emphasises that efficient testing can be accomplished by using refined models, grouped in libraries.
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