TMR-logic-based LUT for quickly wake-up FPGA

Abstract

A new look-up-table (LUT) circuit combined with tunneling magneto-resistive (TMR) devices and MOS transistors is proposed for a power-aware FPGA, where the standby mode can be quickly changed to the active one. Since a TMR device is regarded as a variable resistor, any logic functions with external inputs and one-bit stored input can be performed by series and/or parallel connection of TMR devices and MOS transistors, which achieves a compact circuit implementation. The use of TMR-based logic-circuit structure makes circuit-configuration information still maintained without external nonvolatile memory even if the power supply is cut off, which realizes an instant standby/active-state capability. The combination of a dynamic current-mode circuitry and the TMR-based logic network also makes it possible to greatly reduce the dynamic power dissipation. A typical arithmetic-circuit design example using the proposed LUTs is discussed, and its advantages in terms of device counts, switching delay and power dissipation are demonstrated in comparison with a corresponding SRAM-based FPGA with external nonvolatile memory.