Timing penalties associated with cache sharing

Abstract

Although important from software performance perspective, the behavior of memory caches is not captured by the common approaches to modeling of software performance, where the software performance models tend to treat operation durations as constants despite the fact that the operations compete for memory caches. Incorporating memory cache models into software performance models is hindered by the fact that existing cache models do not provide information about timings and penalties, but only about hits and misses. The paper outlines the relationship of cache events and cache timings on a real computer architecture, indicating that the existing practice of modeling cache miss penalties as constants is not sufficient to model software performance faithfully.