Timing Jitter Modeling and Minimization for a Servo Track Writer

Abstract

During servo track writing (STW), the timing jitter in clocking process can induce significant errors on servo pattern, named as phase-in error. In this paper, we measured the timing jitter on our STW experimental setup and modeled the jitter sources in frequency domain. With the timing jitter sources models, the typical phase-locked loop system is looked as a typical closed-loop control system and H2 control method is used to design the loop filter with objective to minimize the timing jitter after the output of voltage control oscillator (VCO). The simulation results show that timing jitter can be significantly reduced with loop filter designed with the H2 method