Timing distribution for the Belle II data acquistion system

Abstract

At Belle II, detector signals are digitized inside or near the detector and collected via high-speed optical serial links. Each frontend digitization board equips an FPGA for a unified data link and timing system interface to receive the system clock, the level-1 trigger, other fast timing signals and to return status signals. Timing signals are serialized and delivered via a commodity category-7 LAN cable, through a tree-structure distribution network made from cascaded 1-to-20 distribution modules. We report the performance of this timing distribution system.