Timing and Synchronization for Explicit FSM Based Traffic Light Controller

Abstract

Traffic light control unit can be designed as a synchronous sequential machine with finite number of states. Explicit finite state model is used to design the necessary coding for control system using Verilog HDL. The machine is modelled with only six states and these states are chosen based on the traffic control algorithm. In each state necessary delay is provided and for that particular delay the necessary traffic lights are set ON and OFF. For illustration just only two roads are chosen and control algorithm controls the traffic lights of that roads. This paper proposes a flexible framework which provides a delay in particular state using clock divider, also discusses the issue of modelling the state machine in a synthesis friendly manner. The design is aimed for Xilinx Spartan-6 XC6LX16- CS324 FPGA. Also this paper discusses the issue of choosing a state encoding scheme.