Timing and power model for CMOS inverters

Abstract

Nowadays, the delay, the output transition time and the short circuit power consumption of CMOS gates depend on the load capacitance and the input transition time. In currently used technology libraries, table models with 25 or more samples are used for calculating by interpolation each of these three variables. Previous work deriving analytical models are based on neglecting the short circuit current or approximating currents as piecewise linear. In the beginning of this paper, different mathematical models describing the transistor current are compared with respect to the accuracy of a numerical calculated output waveform. The results show that Sakurai's alpha-Power Model with linear equation in the linear region and exponent alpha=1 serves as a well-fitting model for the underlying 0.35 μm technology. Based on this transistor model and the assumption of a linear rising input, the differential equation of the output voltage, including both transistor currents and the capacitive load, has to be solved. Splitting the solution into regions, an approximate solution can be derived for the case that the PMOS transistor is working in linear and the NMOS in saturation condition. The rather complex calculation of the point where the PMOS transistor switches from linear to saturation region can be simplified by using curve fitting techniques. The required curve parameters depend on technology constants as in MM9 and the quotient wn/wp. Consequently, one set of parameters allows the analysis of a wide range of inverters as long as wn/wp is kept constant. The accuracy of the results for the delay are typically within 10%, those for output transition time and power consumption within 5% compared to spice simulation.