Abstract
In this paper, we examine the impact of using the hierarchy of the design and multiple delay models defined at different abstraction levels to speed up the timing performance evaluation of VLSI circuits. The algorithms implemented in the Dynamic and Hierarchical Timing Analysis (DHTA) tool are described. DHTA rapidly identifies the critical portions of the circuit at high hierarchical levels with rough delay models. These portions are then successively studied at more detailed levels for maximal accuracy. The effects on processing time of exploiting the design hierarchy and using several delay models are characterized. The implementation of DHTA demonstrates experimentally the benefits of using a mixed-mode approach for timing analysis. We show that considering all available hierarchical levels may degrade the computing time and heuristics are proposed to select the hierarchical levels which generally lead to a speed-up.
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