Abstract

This paper presents a 6 bit, 11 MS/s time-interleaved pipeline A/D converter design. The specification process, from block level to elementary circuits, is gradually covered to draw a design methodology. Both power consumption and mismatch between the parallel chain elements are intended to be reduced throughout the design in a CMOS 0.35 μm AMS technology. The goal is accomplished by using some techniques such as double and bottom-plate sampling, fully differential circuits, RSD digital correction and Geometric Programming (GP) optimization of the elementary analog circuits (OTAs and comparators) design. Pre-layout simulations of different blocks and the complete ADC are presented to characterize the designed converter, which consumes 12 mW while sampling a 500 kHz input signal.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.