Timed Petri Net Models of Shared-Memory Bus-Based Multiprocessors

Wlodek M Zuberek

doi:10.4236/jcc.2018.610001

Abstract

In shared-memory bus-based multiprocessors, when the number of processors grows, the processors spend an increasing amount of time waiting for access to the bus (and shared memory). This contention reduces the performance of processors and imposes a limitation of the number of processors that can be used efficiently in bus-based systems. Since the multi-processor’s performance depends upon many parameters which affect the performance in different ways, timed Petri nets are used to model shared-memory bus-based multiprocessors at the instruction execution level, and the developed models are used to study how the performance of processors changes with the number of processors in the system. The results illustrate very well the restriction on the number of processors imposed by the shared bus. All performance characteristics presented in this paper are obtained by discrete-event simulation of Petri net models.

Highlights

More than 50 years ago Gordon Moore predicted that the number of transistors on microprocessor chips will double every 18 to 24 months
Since the multiprocessor’s performance depends upon many parameters which affect the performance in different ways, timed Petri nets are used to model shared-memory bus-based multiprocessors at the instruction execution level, and the developed models are used to study how the performance of processors changes with the number of processors in the system
This paper is an extension of previous work on performance analysis of shared-memory bus-based multiprocessors using timed Petri nets [10]

Summary

Introduction

More than 50 years ago Gordon Moore predicted that the number of transistors on microprocessor chips will double every 18 to 24 months (the so called Moore’s law [1]). In order to study the influence of different parameters on the performance of the system, a model of a pipelined processor at the instruction execution level is proposed and is used for performance analysis of shared-memory bus-based multiprocessors. In order to study performance aspects of systems modeled by Petri nets, the durations of modeled activities must be taken into account This can be done in different ways, resulting in different types of temporal nets [8]. In this paper, timed Petri nets are used to model shared-memory bus-based multiprocessor systems at the level of instruction execution. This paper is an extension of previous work on performance analysis of shared-memory bus-based multiprocessors using timed Petri nets [10]. Much simpler models of multiprocessor systems are presented in this paper with performance characteristics that are consistent with previous models

Timed Petri Nets

Pipelined Processors

Shared-Memory Bus-Based Systems

Findings

Concluding Remarks