Abstract
This paper presents the design of a time-to-digital converter (TDC) suitable for a 3.5-GHz all-digital phase-lock loop (PLL). The converter is based on a digital bang-bang delay-lock loop, which allows constant resolution over process and temperatures spreads, avoids an off-chip filter and guarantees fast lock. The clock rate of the digital filter is scaled down by eight from the 3.5-GHz input to allow its implementation with standard cells. The occurrence of a limit cycle is analytically predicted and properly minimized, and its effect on the PLL phase noise is discussed. The circuit fabricated in 90-nm CMOS entails 16 delay stages, which lock to the input frequency in the 2.9-3.9-GHz range (limited by the available signal source). The delay of each TDC cell can be controlled with 50-fs step and the TDC time resolution is 16 ps at 3.9 GHz. The power consumption ranges between 8.1 and 16.5 mW, respectively. The limit-cycle-induced spur is below - 50 dBc. The area occupation is 0.032 mm2.
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