Time-resolved simulation of the negative capacitance stage emerging at the ferroelectric/semiconductor hetero-junction

Abstract

Recently, a number of papers have demonstrated sub-60 mV/decade switching by using the negative capacitance (NC) effect in ferroelectric-gate FETs. However, the physical picture is not yet understood. In this paper, an alternative physical picture for emerging NC is proposed and the development of the NC stage at the ferroelectric/semiconductor hetero-junction is described. Proposed physical picture is based on two factors, 1. “decrease in an additional voltage originated from the depolarization field by surface potential of semiconductor” and 2. “Change in the distribution ratio of gate voltage (VG) to voltage applied to the ferroelectric layer (VF) and surface potential of the semiconductor (ψS) due to the capacitance change of semiconductor.” With considering these two essential phenomena, time-resolved simulations of the NC stage emerging at the ferroelectric/semiconductor hetero-junction were carried out. This NC phenomena expressed by the negative differential of the DF for the VF, i.e. (∂DF/∂VF<0), emerging in the MFS (metal/ferroelectric/semiconductor) capacitor without inserting dielectric layer, are dynamically simulated to discuss the proposed NC process. The simulation results clearly reveal that the NC stage is originated from the existence of additional voltage caused by the depolarization field by surface potential of semiconductor originated from the existence of remanent polarization of ferroelectric layer, and change in the capacitance of the semiconductor during polarization switching. The different physical picture from steady-state NC and transient NC can be clearly shown.