Time-Interleaved Multirate Sigma–Delta Modulators

Abstract

A time-interleaved (TI) implementation of multirate sigma-delta modulators (SDMs) is proposed. In multirate SDMs, the first integrator is clocked at a rate that is lower than that of the rest of the integrators. In the proposed architecture, each integrator clocked at a high rate is replaced by two parallel integrators operating in interleaved mode and clocked at the same low rate as the first one. The new architecture has several nice features. First, every integrator operates at the same low rate, which simplifies the clock circuitry when compared to the original multirate modulator. Second, there are no delayed cross paths, which is typical of TI-SDMs. Third, no high-rate sample-and-hold at the input of a TI-SDM is required. Finally, as time interleaving is not applied to the first integrator, the proposed modulator is robust against circuit mismatches, unlike other TI architectures. The same strategy can be applied to continuous time (CT) modulators. To the authors' knowledge, this is the first TI-CT-SDM ever reported