Time-Interleaved and Circuit-Shared Dual-Channel 10 b 200 MS/s 0.18 $\mu{\rm m}$ CMOS Analog-to-Digital Convertor

Abstract

This paper proposes a 10 b 200 MS/s pipeline analog-to-digital convertor (ADC) for high-quality video systems based on double-channel and op-amp sharing schemes to minimize power consumption and channel mismatch. The double channel time-interleaved scheme reduces the required operating speed of amplifiers in the sample-and-hold amplifier and multiplying digital-to-analog (D/A) converters by 50%. The switched and shared op-amp with two input pairs amplifies each channel signal without extra series switches while minimizing the gain, bandwidth and offset mismatches between channels. The low-jitter sampling clock with a 50% duty cycle improves the dynamic performance of the wideband input signals significantly. The Flash ADCs employ a differential difference amplifier type pre-amp to continuously process dual-channel outputs. The prototype ADC in a 0.18 μm CMOS technology demonstrates the measured differential nonlinearity and integral nonlinearity within 0.62 and 0.99 LSB, respectively. At 200 MS/s, the ADC shows a maximum SNDR of 52.8 dB and a maximum SFDR of 60.4 dB. The ADC with an active die area of 1.28 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> consumes 54.0 mW at 1.8 V.