Time-Gated and Multi-Junction SPADs in Standard 65 nm CMOS Technology

Abstract

SPADs (Single-Photon Avalanche Diodes) are important detectors for a wide range of applications including positron emission tomography, Raman spectroscopy, light detection and ranging, and quantum key distribution. For some applications, custom image sensor technologies are used, but at a higher cost and lower performance imagers when compared to implementation in a standard planar CMOS technology. In this paper, we explore time-gating and multi-junction techniques to improve the SPAD's performance in smaller standard planar CMOS processes to take advantage of their potential for monolithic integration with other advanced, mixed-signal circuitry for simple, low-cost, high-performance imaging solutions. A passively quenched, unbuffered, triple-junction SPAD structure was designed in a standard 65 nm CMOS process from TSMC. The characterization of the SPAD junctions in this process is the first in literature and proves useful for SPAD designers aiming for advanced CMOS technology nodes. The time-gated (TG) pixel design used the top shallow junction. The potential for improved photon detection efficiency and wavelength distinction through a multi-junction design was investigated. Our testing demonstrated that the proposed implementation of the triple-junction SPAD in this technology node is not suitable for wavelength distinction. The TG design achieved a fill-factor of 28.6%, and at an excess voltage of 300 mV, it achieved a peak photon detection efficiency of ~2.1% at 440 nm, <; 1% afterpulsing probability for hold-off times >22 ns, and <; 200 ps timing jitter.