Abstract
We propose a new digital-to-analog converter (DAC) for realizing a synapse circuit in mixed-signal spiking neural networks. We refer to this circuit as a “time-domain DAC (TDAC)”. It produces weights for converting a digital input code into voltage using one current waveform. Therefore, the TDAC is more compact than a conventional DAC consisting of many current sources and resistors. Moreover, a TDAC with leak resistance reproduces biologically plausible synaptic responses expressed as alpha functions or dual exponential equations. We also present numerical analysis results for a TDAC and circuit simulation results for a circuit designed using the TSMC 40 nm CMOS process.
Highlights
Application-specific integrated circuits (ASICs) for neuromorphic hardware have been studied intensively with the aim of achieving highly efficient computation [2,5,11,18, 20,25]
To realize highly efficient neuromorphic hardware with reusable synaptic weights that is fabricated using conventional complementary metal–oxide–semiconductor (CMOS) technology, synaptic weights of the circuit architecture can be stored in digital memory and MAC operations can be achieved by an analog circuit; in other words, a mixed-signal architecture is suitable
We proposed a new digital-to-analog converter (DAC), called a time-domain DAC (TDAC), in which the weight of each bit that codes for the DAC is realized by a current waveform sampled using non-overlapping digital signals
Summary
Application-specific integrated circuits (ASICs) for neuromorphic hardware have been studied intensively with the aim of achieving highly efficient computation [2,5,11,18, 20,25]. To realize highly efficient neuromorphic hardware with reusable synaptic weights that is fabricated using conventional complementary metal–oxide–semiconductor (CMOS) technology, synaptic weights of the circuit architecture can be stored in digital memory and MAC operations can be achieved by an analog circuit; in other words, a mixed-signal architecture is suitable. Realizing a mixed-signal circuit that has multi-bit synaptic weights is important for achieving on-chip learning, but it is difficult to realize high-integration and highly efficient neuromorphic hardware because conventional multi-bit DACs comprise many current-source circuits or resistor arrays, thereby necessitating a large footprint and high power consumption [14,17]. To implement high-integration and highly efficient mixed-signal SNN hardware with on-chip learning having multi-bit synaptic weights, a suitable DAC architecture is one with neither resistors nor capacitors, or one but with few CEs, the number of which does not increase with the number of bits.
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