Abstract

A novel approach to testing CMOS digital circuits is presented that is based on an analysis of voltage transients at multiple test points and I/sub DD/ switching transients on the supply rails. We present results from hardware experiments that show distinguishable characteristics in the transient waveforms of defective and nondefective devices. These variations are shown to exist in both the time domain and frequency domain for CMOS open-drain and bridging defects, located both on and off sensitized paths.

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