TIGER: an efficient timing-driven global router for gate array and standard cell layout design

Abstract

In this paper, we propose an efficient timing-driven global router, TIGER, for gate array and standard cell layout design. Unlike other conventional global routing techniques, interconnection delays are modeled and included during the routing and rerouting process in order to minimize the maximum channel density for gate arrays or the total track number for standard cells, as well as to satisfy the timing constraints in TIGER. The timing-driven global routing problem is formulated as a multiterminal, multicommodity network flow problem with integer flows under additional timing constraints. Two novel performance-driven Steiner tree algorithms are proposed to generate the initial global routing trees. A critical-path-based timing analysis method is used to guarantee the satisfaction of timing constraints. Experimental results based on MCNC (ISCAS) benchmarks show that TIGER can obtain better results than or comparable results with TimberWolf 5.6.