TID-Tolerant Inverter Designs for Radiation-Hardened Digital Systems

Abstract

This work experimentally compares total ionizing dose (TID) effects on various inverter designs, which are fundamental components for implementing radiation hardening by design (RHBD) digital circuits. Based on prior works, which reported that leakage current variation of NMOS transistors is significantly larger than that of PMOS, this work suggests design methodologies to alleviate TID effects on NMOS transistors with the following inverter topologies: stacked NMOS inverter, pseudo PMOS inverter, PMOS-only inverter, and dummy transistor inverter. We have also investigated different sizes of the inverters as well as different PN ratios to optimize them for a more robust design that can operate under high radiation environments. These designs are fabricated in the 180 nm CMOS process and measured performance degradations by using a 60Co source. Experimental results show that the stacked NMOS inverter provides best performance in terms of switching point variation, area, and power consumption. In addition, one with larger transistor size and PN ratio is more helpful in TID hardening. Given that an inverter is an essential and basic building block of digital systems, the proposed techniques can be adopted in any systems requiring operation under radiation-emitting circumstances, e.g., measurement devices in nuclear power plants or electronics in space.