Throughput Considerations for In-Situ Doped Embedded Silicon Carbon Stressor Selectively Grown into Recessed Source Drain Areas of NMOS Devices

Abstract

In this paper we calculate throughput based on recipe overhead (chamber etch, wafer load, wafer bake, cool down, unload) and deposition time for "true" SEG or the core cycle time (deposition, purge, etch, purge times) for a CDE process. In the latter case an average, effective growth rate (GR) can be extracted by dividing the deposited thickness per cycle by the cycle time. In high volume manufacturing (HVM) high SEG GR are necessary for high throughput and low Cost of Ownership (CoO). High GR also enable high substitutional carbon levels [C]sub in dilute Si:C alloys. In this work all experiments were exclusively performed using Silcore® (ASM trademarked version of Si3H8). Due to the high GR at low process temperature, high [C]sub and low films resistivities can be obtained independent of the two different Cl containing etch chemistries that were used in this study. The main challenge of using Cl2 compared to the ASM proprietary etch chemistry is the 25-30 times lower etch rate selectivity (~7 vs. ~190) of a-SiCP over epi-SiCP. As a result of the low etch rate selectivity using a Cl2 etch chemistry, a significant portion of the epitaxial SiC:P is also etched with the a-SiCP. This results in a low effective growth rate which has a deleterious impact to throughput.