Abstract
Through Silicon Vias (TSV) can provide high density inter-strata connections with reduced signal delay and power consumption for stacked multi-chip interconnection and packaging. Among the various process steps to form a TSV, filling of the via with metal is the most difficult and costly for high aspect ratio features. A robust TSV filling by electroplating requires continuous seed coverage and plating conditions that result in void free filling. Discontinuous seed can result from ledges and overhangs when reentrant TSV hole profiles form. Such TSVs are filled by creating electrical continuity through one of the two methods (a) electroless seed enhancement of the discontinuous copper seed or (b) by the deposition of a thin film of TiN prior to the barrier and seed. Both plating process conditions and bath composition are optimized to achieve void free filling of TSVs of various geometries.
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