Abstract
Inspired from Through Silicon Vias (TSVs), Through Silicon Capacitors (TSCs) are newly developed and integrated throughout silicon interposers. Thanks to the use of the third dimension in the silicon interposer, TSC technology allows to obtain high capacitance density, up to 56 nF/mm2. This paper deals with a demonstrator to investigate the impact of large matrices of TSCs (13×13 TSCs) on the electrical performance of Power Distribution Networks (PDN). First, the frequency response of TSCs matrix is modeled from DC to 10 GHz. Next, extracted spice models are used to simulate the PDN impedance of a typical processor circuit. Finally a transient analysis is performed to evaluate the performance of the PDN in the time domain. TSCs allow to reduce considerably voltage ripples on the PDN and one obtained less than 10% of voltage ripples for a total capacitance of 1.4 µF.
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